Freescale Semiconductor /MK70F12 /DDR /CR07

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CR07

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKPW0TCKESR0 (0)AP 0 (0)CCAPEN

AP=0, CCAPEN=0

Description

DDR Control Register 7

Fields

CLKPW

Clock Pulse Width

TCKESR

Time Clock low Self Refresh

AP

Auto Precharge

0 (0): Disabled

1 (1): Enabled

CCAPEN

Concurrent Auto-Precharge Enable

0 (0): Disabled

1 (1): Enabled

Links

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